The present invention relates to a programmable logic device in which circuit specifications original to circuit designers can be incorporated easily. The invention further relates to a programmable logic device suitable for forming internally and efficiently a sequential circuit necessary for sequential controllers, signal generators and the like.
As is well known, by use of a programmable logic device, it is possible to realize a suitable logic circuit having an AND-OR two-stage structure by programming lattice points of logical product and logical add matrices. The device is excellent in use for general purposes.
Not only can the programmable logic device be used as a random logic device, but the device can also be used as a controller such as, for example, a sequential controller because a desired sequential circuit can be provided by feeding the output of the logical add matrix to the input side of the logical product matrix.
In general, a conventional programmable logic device has such a configuration as shown in FIG. 1. As shown in FIG. 1, the conventional device has a logical product matrix having input signal lines L.sub.1 -L.sub.n represented by a group of vertical lines in the drawing and logical product term lines l.sub.1 -l.sub.n arranged to intersect the input signal lines and represented by a group of horizontal lines in the drawing and being provided for the purpose of attaining a desired logic circuit by suitably programming lattice points formed at the intersections thereof, and a logical add matrix (functionally represented by multiple-input gates OR.sub.1 -OR.sub.i in the drawing) conjugated through the logical product output (functionally represented by AND gates in the drawing) produced in the logical product term lines l.sub.1 -l.sub.n. Further, there are provided general input ports I.sub.1 -I.sub.j for supplying logic signals from the outside to a part of the input signal lines L.sub.1 -L.sub.n, a clock input terminal CLK for receiving a clock signal supplied thereto, and a control signal input terminal CNT for receiving a control signal supplied thereto. Further, output ports are formed for the purpose of feeding the output signals of the logical add matrix (multiple-input OR gates OR.sub.1 -OR.sub.i in the drawing) to the outside.
In the following, the output circuit as related to an output terminal P.sub.1 in the output ports is described representatively. A certain logical add output (for example, OR.sub.1) is connected to a data-input contact D of a D-type flip-flop circuit FF.sub.1. An output contact Q of the flip-flop circuit is connected to an output terminal P.sub.1 through an output buffer circuit B.sub.1. A clock-input contact of the flip-flop circuit FF.sub.1 is arranged so as to receive the clock signal from the clock-input terminal through an input buffer circuit. An output buffer circuit FB.sub.1 operates corresponding to the logical level of the flip-flop circuit FF.sub.1 so that the output signal of the flip-flop circuit FF.sub.1 is transmitted to the output terminal P.sub.1 or is turned to a high-impedance state. Further, the flip-flop circuit FF.sub.1 is arranged so that the inverted output Q thereof is fed back to a part of the input signal lines L.sub.1 -L.sub.n through the buffer circuit FB.sub.1. The output circuit as related to the other output terminals P.sub.2 -P.sub.k has the same construction as described above. In short, the output circuit has a cell structure.
For example, in the case where a signal generator for generating various kinds of digital signals different in frequency, phase and waveform and suitable for use of various kinds of electronic appliances is prepared by use of a conventional programmable logic device having the aforementioned structure, complex signals are formed by programming suitable lattice points of the logical product matrix to thereby form a shift-register or counter from the flip-flop circuits formed within the output circuit and, at the same time, by feeding the output thereof back to the logical product matrix.
However, a limitation in the number of bits (the number of flip-flop circuits) occurs in the conventional programmable logic device shown in FIG. 1 when various kinds of signals are generated, because the shift-register or counter is constituted within the output circuit by a plurality of flip-flop circuits each having a 1-bit structure. In most cases, it is difficult to form the signal generator by one programmable logic device. In general, the flip-flop circuit is designed to serve as a register for temporally registering the output signal before transmitting it to a corresponding output terminal. Accordingly, when the flip-flop circuits are used as the shift-register or counter, a great number of output terminals are left without use. Accordingly, there arises a problem in that efficiency in use of internal resources becomes poor, in that shortage of output ports occurs or in that the degree of freedom in design is lowered.
Further, as shown in FIG. 1, signals are always fed back to the logical product matrix through the multiple-input OR gates (OR.sub.1 -OR.sub.i) provided in the output side of the logical add matrix. Accordingly, delay of signal transmission caused by the delay time of these OR gates occurs. Consequently, it is difficult to form fine-timing and high-frequency signals to overcome the delay time.
Another conventional device is shown in FIG. 2. The conventional device of FIG. 2 has a structure in which input signals I.sub.1 -I.sub.j from general input ports are fed to input signal lines L.sub.A1 -L.sub.Aj, L.sub.B1 -L.sub.Bj of the
logical product matrix through buffer circuits B.sub.1 -B.sub.j after being inverted or not being inverted. At the same time, the AND operation matrix 1 has input signal lines L.sub.F1 -L.sub.Fk, L.sub.D1 -L.sub.Dk for receiving feedback signals from the output side (which will be described later). Further, the ends of logical product term lines l.sub.1 -L.sub.n intersecting these signal lines are connected to a group of input signal lines of the logical add matrix 2. Logical add term lines g.sub.1 -g.sub.k intersecting the group of input signal lines are respectively connected, through OR gates OR.sub.1 -OR.sub.k, to the input contacts D of flip-flop circuits FF.sub.1 -FF.sub.k provided within the output circuit. The outputs (for example, the inverted outputs in the drawing) of the flip-flop circuits FF.sub.1 -FF.sub.k are fed back to the input signal lines L.sub.F1 -L.sub.Fk, L.sub.D1 -L.sub.Dk, for example, through buffer circuits F.sub.1 -F.sub.k.
The logical add term lines g.sub.1 -g.sub.k represented by the solid line in the drawing show a desired number of signal lines. Each of the OR gates OR.sub.1 -OR.sub.k has a plurality of input contacts corresponding to the number of signal lines. The symbols a.sub.1 -a.sub.n designating AND gates functionally show the fact that logical products are obtained by programming lattice points (represented by "" in FIG. 2 which will be described later. Of course, the AND gates are not formed individually in the respective ends of the logical product term lines.
Intersections or lattice points of the respective signal lines in the logical product matrix 1 and the logical add matrix 2 are programmed suitably to perform logical products and logical adds (by the logical product matrix in the case of a fixed-type OR matrix having lattice points programmed in advance) to thereby make these matrices 1 and 2 serve as decoders or the like. As described above, the device has a structure in which a predetermined circuit can be realized.
However, the conventional programmable logic device shown in FIG. 2 has the following problems
The internally provided flip-flop circuits are provided to serve as registers for temporally registering output signals mainly to transmit the signals to output ports. In short, the flip-flop circuits are formed within the output circuit as shown in FIG. 2. Accordingly, in the case where these flip-flop circuits are used as a sequential circuit, output ports connected to the output contacts of the flip-flop circuits in advance are left without use. There arises a problem in effective use of the internal resources, shortage of output ports, and the like.
In the case where a binary counter is formed by programmably connecting these flip-flop circuits to decode the outputs (Q, Q') of the respective flip-flop circuits, glitch occurs in a point in which all output signals of the respective flip-flop circuit change simultaneously from "0" to "1" or from "1" to "0", as is well known. The glitch brings malfunction or the like within the circuit. Accordingly, there arises a problem in that circuits for removing the glitch must be considered in circuit design.